1. Technical Field
The present invention relates to a chip package structure and a manufacturing method thereof. More particularly, the present invention relates to a chip package structure and a manufacturing method both being capable of accomplishing favorable heat dissipating efficacy and improving manufacturing yield.
2. Description of Related Art
With rapid advance in technologies, integrated circuits (ICs) have been extensively used in out daily lives. Typically, IC manufacturing can be roughly classified into three main stages: a silicon wafer fabrication stage, an IC fabrication stage, and an IC package stage.
At present, a technique by applying which a plurality of chips are stacked and then packaged has been developed. Nonetheless, the chip stacked structure frequently encounters an issue of unsatisfactory heat dissipation, which further restricts the number of the stacked chips. Moreover, during a process of packaging the chips, the chips are first stacked and then packaged, which is apt to result in unfavorable production yield.